Temperature compensated video signal processing circuit with a video signal clipping device

ABSTRACT

A temperature dependent variation of the voltage drop across a clipping pn junction device which causes the clipping voltage level of a DC restored video signal to vary is compensated by the base-to-emitter voltage variation of an emitter follower transistor having substantially the same temperature characteristic as the clipping pn junction device. A variation in the DC level of the DC restored video signal resulting from the base-to-emitter voltage variation of the emitter follower transistor is compensated by a feed back type differential amplifier whose output is fed back to one input thereof through an emitter follower transistor and a pn junction device.

This invention relates to a video signal processing circuit and in particular to a video signal processing circuit with a video signal clipping device.

In a DC coupled video signal processing circuit having a clipping diode for clipping a DC restored video signal, a clipping voltage level is varied by temperature dependent variation of the forward voltage drop across the clipping diode. Such a variation in the level of voltage can be neglected by making the amplitude level of the video signal relatively great. However, such a method can not be utilized in a monolithic bipolar integrated circuit in which a signal of great amplitude can not be processed.

The object of this invention is to provide a DC coupled video signal processing circuit suitable for integrated circuit version, which is capable of compensating variation in the clipping level of a DC restored video signal which results from the variation of forward voltage drop across a clipping diode with temperature and capable of compensating variation in the DC level of the DC restored video signal which is caused by the compensation for variation in the clipping level of the video signal.

According to this invention there is provided a video signal processing circuit comprising a first transistor differential amplifier having an input and output, the input of the first transistor differential amplifier being connected to receive a DC restored video signal; a clipping pn junction device coupled to the output of the first transistor differential amplifier; a first emitter follower transistor whose base is connected to a bias voltage source to apply a predetermined bias voltage to the clipping pn junction device by the emitter output of said first emitter follower transistor; and a second transistor differential amplifier including first and second transistors each having an emitter, collector and base and connected in common emitter configuration, the base of the first transistor being coupled to the output of the clipping pn junction, a load resistor coupled to the collector of the second transistor, a second emitter follower transistor whose base is coupled to the collector of the second transistor, and a second pn junction device coupled between the emitter of said second emitter follower transistor and the base of the second transistor, the polarity relation of the second pn junction device to the base of the second transistor being the same as that of the clipping pn junction device to the base of the first transistor.

This invention will be further described by way of example by reference to the accompanying drawing which shows schematically a video signal processing circuit according to one embodiment of this invention.

In the drawing, transistors Q₁ and Q₂ are connected in common emitter configuration to constitute a first differential amplifier A₁. The emitters of the transistors Q₁ and Q₂ are grounded through a constant current source I₁. The collector of transistor Q₁ is connected to a DC power supply terminal T₂, while the collector of transistor Q₂ is connected through a load resistor R₁ to the DC power supply terminal T₂. The base of transistor Q₂ is connected to a junction between resistors R₁ and R₃ which are series connected between the DC power supply terminal T₂ and ground. The base of transistor Q₁ is connected to an input terminal T₁ where a DC restored video signal is received.

A clipping pn junction device such as a diode-connected transistor Q₃ (with the collector shorted to the base) is DC coupled to the output of the first differential amplifier A₁ i.e. a junction between the load resistor R₁ and the collector of transistor Q₂. That is, the collector and base of transistor Q₃ are coupled to the output of the first differential amplifier A₁.

A transistor Q₄ has the collector connected to the DC power supply terminal T₂ and the emitter grounded through a load resistor R₅ i.e. is connected in emitter follower configuration. The emitter of transistor Q₄ is connected through a resistor R₄ to the emitter of transistor Q₃ and the base of transistor Q₄ is connected to a clip level setting voltage source.

Transistors Q₅ and Q₆ are connected in common emitter configuration to constitute a second differential amplifier A₂. The emitters of transistors Q₅ and Q₆ are grounded through a constant current source I₂. The collector of transistor Q₅ is connected to the DC power supply terminal T₂ while the collector of transistor Q₆ is connected through a load resistor R₆ to the DC power supply terminal T₂. One input of the second differential amplifier A₂ i.e. the base of transistor Q₅ is DC coupled to the emitter of clipping transistor Q₃.

To the output of the second differential amplifier A₂ i.e. a junction between the load resistor R₆ and the collector of transistor Q₆ is DC coupled the base of a transistor Q₈ which has the collector connected to the DC power supply terminal T₂ and the emitter grounded through a load resistor R₈ i.e. is connected in emitter follower configuration. The emitter of the transistor Q₈ is coupled to an output terminal T₃. To the emitter of transistor Q₈ is DC coupled the base of a transistor Q₇ which has the collector connected to the DC power supply terminal T₂ and the emitter grounded through a load resistor R₇ i.e. is connected in emitter follower configuration. The emitter of transistor Q₇ is DC coupled to the other input of the second differential amplifier A₂ i.e. the base of transistor Q₆.

The operation of the above-mentioned circuit will now be explained below.

The DC restored video input signal is amplified by the first differential amplifier A₁ to generate an amplified output whose block level is clipped by the clipping transistor Q₃.

The clip level of the video signal is determined by the emitter voltage of the emitter follower transistor Q₄ operative to apply a bias voltage to the clipping transistor Q₃. The emitter voltage is lower than the clip level setting voltage applied to the base of transistor Q₄, by the base-to-emitter voltage of the transistor Q₄. The clip level is controlled by the voltage applied to the base of transistor Q₄. When a video signal having a voltage level greater than the clip level is applied to the base of transistor Q₅, it appears at the collector of transistor Q₆. The output video signal may be DC coupled from the output terminal T₃ to a utilization circuit, for example, a color coder, through the emitter follower transistor Q₈ having a low output impedance. The output video signal is also fed back to the base of transistor Q₆ through the emitter follower transistor Q₇. That is, since the output of the second differential amplifier A₂ is fed back to the input terminal thereof through the emitter follower transistors Q₇ and Q₈, the second differential amplifier A₂ has a gain of unity. The feedback type differential amplifier having a gain of unity performs an important function in the invention.

Now consider the case where the base-to-emitter voltage of the clipping transistor Q₃ is varied by the change in ambient temperature.

The clip level of the video signal tends to be varied by the variation of the base-to-emitter voltage of the clipping transistor Q₃. Since, however, the emitter voltage of the transistor Q₄ which is lower than the clip level setting voltage by the base-to-emitter voltage of the transistor Q₄ is applied through the resistor R₄ to the emitter of clipping transistor Q₃, the variation of the clip level is cancelled. Where use is made, as the transistor Q₃ and Q₄, of matched pair having a substantially identical temperature characteristic, the base-to-emitter voltages V_(BE) of both the transistors Q₃ and Q₄ likewise vary. In consequence, the voltage at the emitter of transistor Q₄ varies with the same magnitude as, and in a direction opposite to, the base-to-emitter voltage of the clipping transistor Q₃ with respect to the clip level setting voltage taken as a reference, permitting the base-to-emitter voltage variations of the transistors Q₃ and Q₄ to be cancelled with respect to each other. This means that the clip level of the video signal is maintained constant irrespective of the temperature variation.

It will be evident, however, that the emitter voltage of the clipping transistor Q₃ i.e. the base voltage of the transistor Q₅ is caused to be varied by the above-mentioned compensation for the clip level variation i.e. by the variation of the base-to-emitter voltage V_(BE) of the transistor Q₄. This means, the DC voltage level of the video signal varies with change in temperature.

The DC voltage level variation of the video signal can be compensated as follows.

Let the base voltage of the transistor Q₅ be represented by -V_(BE) (in this case, consideration is restricted only to its variation component). It is because that the base voltage of the transistor Q₅ is lower than the predetermined clip level setting voltage by the base-to-emitter voltage V_(BE) of the transistor Q₄ or the variation voltage component. In this case, the emitter voltage of the transistor Q₅ is lower than the base voltage thereof by the base-to-emitter voltage V_(BE) of transistor Q₅, i.e. is -2V_(BE). On the other hand, the base voltage of the transistor Q₆ is higher than the emitter voltage thereof by the emitter-to-base voltage V_(BE) of transistor Q₆ i.e. is -V_(BE). The emitter voltage of the transistor Q₇ is the same as the base voltage of the transistor Q₆. Consequently, the base voltage of the transistor Q₇ is higher than the emitter voltage thereof by the base-to-emitter voltage V_(BE) of transistor Q₇. From the above explanation it will be understood that the variation component V_(BE) disappears at the base of transistor Q₇.

Since the base of transistor Q₇ is connected to the output terminal T₃, it is possible to obtain an output video signal free from any variation of a DC voltage level which would occur due to the variation of the base-emitter voltage of the emitter follower transistor Q₄ adapted to compensate for the variation of the clip level. The output video signal may be DC coupled to a next stage circuit such as, for example, a color coder, the feature of which constitutes an outstanding advantage of this invention.

According to this invention the emitter output of the emitter follower transistor Q₈ may be coupled through a pn junction to the base of transistor Q₆. For this reason, the emitter follower transistor Q₇ may be replaced by a pn junction device such as a diode or a diode-connected transistor. However, the result of an experiment reveals that, for the purpose of enhancing frequency characteristic of the circuit, it is desirable to use the emitter follower configuration as shown in the drawing which couples the emitter of transistor Q₈ to the base of transistor Q₆ by the base-emitter pn junction.

As, with a monolithic integrated circuit, transistors of very uniform characteristics (including a temperature characteristic) can be formed on a semiconductor substrate, the temperature characteristic of the clipping transistor Q₃ can be made equal to that of the compensating transistor Q₄. Furthermore, the temperature compensated video signal processing circuit according to this invention is very suitable for integrated circuit version, since the video signal need not be treated with a great amplitude. 

What we claim is:
 1. A video signal processing circuit comprising:a first transistor differential amplifier having an input and output, the input of said first transistor differential amplifier being connected to receive a DC restored video signal; a clipping pn junction device coupled to the output of said first transistor differential amplifier; a first emitter follower transistor whose base is connected to a bias voltage source to apply a predetermined bias voltage to said clipping pn junction device by an emitter output of said first emitter follower transistor; and a second transistor differential amplifier including first and second transistors each having an emitter collector and base and connected in common emitter configuration, the base of said first transistor being coupled to the output of said clipping pn junction, a load resistor coupled to the collector of said second transistor, a second emitter follower transistor whose base is coupled to the collector of said second transistor, and a second pn junction device coupled between the emitter of said second emitter follower transistor and the base of said second transistor, the polarity relation of said second pn junction device to the base of said second transistor being the same as that of said clipping pn junction device to the base of said first transistor.
 2. A video signal processing circuit according to claim 1 in which said clipping pn junction device is a diode-connected transistor whose collector and base are connected with each other.
 3. A video signal processing circuit according to claim 1 in which said second pn junction device comprises an emitter follower transistor whose base is coupled to the emitter of said second emitter follower transistor and whose emitter is coupled to the base of said second transistor.
 4. A video signal processing circuit according to claim 1 in which said clipping pn junction device is a diode-connected transistor whose collector and base are connected with each other, said diode-connected transistor having the collector and base coupled to the output of said first differential amplifier and an emitter coupled to the base of said first transistor of said second differential amplifier, and the emitter of said first emitter follower transistor. 